It can be appreciated that different areas of semiconductor devices can. operate at different voltage levels. For example, in a mixed signal design an isolated p well and an n isolation ring may operate at voltages different from that of the global substrate, for example. Accordingly, it can be appreciated that it is important to test the different areas to see if they comply with respective voltage rules. Such voltage rules are generally implemented in software that is applied to a proposed design layout. Stated another way, a proposed layout (e.g., for a mixed signal circuit) is run through certain voltage dependent design rule software whereby a ‘red flag’ is raised if certain voltage rule requirements are not met or certain voltage rules are otherwise violated.
Nevertheless, conventional schemes for applying voltage rules to different areas of a proposed semiconductor circuit design do not address the interfaces of different areas. This can result in edges of areas being tested under less than adequate voltage rules. Accordingly, it would be desirable to provide a scheme that applies appropriate voltage design rules to area edges.